Liquid crystal display devices (LCDs) characterized by their thin design, light weight and low power consumption have come into widespread use in recent years and are utilized in the display units of mobile devices such as portable telephones (mobile telephones or cellular telephones), PDAs (Personal Digital Assistants) and laptop personal computers. Recently, however, liquid crystal display devices have come to be provided with large-size screens and techniques for dealing with moving pictures have become more advanced, thus making it possible to realize not only mobile applications but also stay-at-home large-screen display devices and large-screen liquid crystal televisions. Liquid crystal display devices that rely upon active matrix drive and are capable of presenting a high-definition display are being utilized as these liquid crystal display devices. The typical structure of an active-matrix liquid crystal display device will be described with reference to FIG. 37. The principal components connected to one pixel of a liquid crystal display unit are illustrated schematically by equivalent circuits in FIG. 37.
In general, a display unit 960 of an active-matrix liquid crystal display device comprises a semiconductor substrate on which transparent pixel electrodes 964 and thin-film transistors (TFTs) 963 are laid out in the form of a matrix (e.g., 1280×3 pixel columns×1024 pixels rows in the case of a color SXGA panel); an opposing substrate on the entire surface of which a single transparent electrode 966 is formed; and a liquid crystal material sealed between these two substrates arranged to oppose each other.
The TFT 963, which has a switching function, is turned on and off under the control of a scan signal. When the TFT 963 turns on, a grayscale voltage that corresponds to a video signal is applied to the pixel electrode 964, and the transmittance of the liquid crystal changes owing to a potential difference between each pixel electrode 964 and opposing-substrate electrode 966. This potential difference is held by capacitance 965 of the liquid crystal, as a result of which an image is displayed.
A data line 962 that sends a plurality of level voltages (grayscale voltages) applied to each pixel electrode 964 and a scan line 961 that sends the scan signal are wired on the semiconductor substrate in the form of a grid (the data lines are 1280×3 in number and the scan lines are 1024 in number in the case of the above-mentioned color SXGA panel). The scan line 961 and data line 962 constitute a large capacitive load owing to the capacitance produced at the intersection of these lines and capacitance, etc., of the liquid crystal sandwiched between the opposing-substrate electrodes.
It should be noted that the scan signal is supplied to the scan line 961 by a gate driver 970, and that the supply of grayscale voltage to each pixel electrode 964 is performed by a data driver 980 via the data line 962.
Rewriting of one screen of data is carried out over one frame ( 1/60 of a second), data is selected successively every pixel row (every line) by each scan line, and a grayscale voltage is supplied from each data line within the selection interval.
Although the gate driver 970 need only supply at least a bi-level scan signal, it is required that the data driver 980 drive the data lines by grayscale voltages of multiple levels that conform to the number of gray levels. To this end, a buffer in the data driver 980 employs a differential amplifier that is capable of outputting highly precise voltages.
With the progress that has been made in raising image quality (increasing the number of colors) in liquid crystal display devices, there is now growing demand for at least 260,000 colors (video data of six bits per each of the colors R, G, B) and preferably 16,770,000 colors (video data of six bits per each of the colors R, G, B) or more.
For this reason, a data driver that outputs a grayscale voltage corresponding to multiple-bit video data requires an output voltage of very high precision. Moreover, there is an increase in the number of elements in the circuitry that processes the video data and an increase in the chip area of the data-driver LSI chip. These invite an increase in cost. This problem will be elaborated below.
FIG. 38 is a diagram illustrating an example of the configuration of the data driver 980 shown in FIG. 37. Here the main portions of the data driver 980 are depicted as blocks. As shown in FIG. 38, the data driver 980 includes a latch address selector 981, a latch 982, a grayscale voltage generating circuit 983, decoders 984 and buffer circuits 985.
The latch address selector 981 decides data latch timing based upon a clock signal CLK. The latch 982 latches video digital data based upon the data latch timing and outputs data to each of the decoders 984 all at once in response to an STB (strobe) signal. The grayscale voltage generating circuit 983 generates grayscale voltages the number of levels whereof corresponds to the video data. The decoders 984 each select and output one grayscale voltage that corresponds to the data input thereto, and the buffer circuits 985, to which the grayscale voltages output from the decoders 984 are applied, subject these voltages to current amplification and output the results as output voltage Vout.
By way of example, if 6-bit video data is input, the number of levels is 64 and the grayscale voltage generating circuit 983 generates grayscale voltages having 64 levels. The decoders 984 select one grayscale voltage from these grayscale voltages of 64 levels.
If 8-bit video data is input, on the other hand, then the number of levels is 256, the grayscale voltage generating circuit 983 generates grayscale voltages having 256 levels and the decoders select one grayscale voltage from these grayscale voltages of 256 levels.
Thus, an increase in the number of bits of video data is accompanied by an increase in the scale of the circuitry of the grayscale voltage generating circuit 983 and decoders 984. For example, if the number of bits is increased from six to eight, the scale of the circuitry increases by four times or more. Accordingly, an increase in the number of bits of video data increases the chip area of the data driver LSI chip and raises cost.
A charge redistribution DAC (digital-analog converter) of the kind shown in FIG. 39 (see Yoshiyuki Takeishi, Edited by Hisashi Hara, “Foundations of MOS Integrated Circuits”, Ultra LSI Introduction Series 5, p. 164, FIG. 5-39, Kindai Kagakusha, May 30, 2002) Non-Patent Document 1) is known as an example of technology for suppressing an increase in the chip area of a data driver LSI chip even if the number of bits is increased. As shown in FIG. 39, the DAC (which is a DAC of the type having a capacitor array and a resistor string) comprises a resistor string; switches S01a to S16a and S01b to S16b that select voltages, which have been extracted from the taps of the resistor string, by higher-order bits (D4 to D7) and supplying the selected voltages to terminals Na and Nb; a switch Sinit that initializes the voltage at a non-inverting input (+) of a voltage follower; and a switch SLSB that selects any one of the voltages that have been supplied to the terminals Na and Nb by lower-order bits (D0 to D3) and supplies selected voltages to four capacitors C/8, C/4, C/2 and C.
In terms of operation of the DAC, two mutually adjacent voltages are selected from among voltages V000, V016, . . . , and V256 of the resistor string by the higher-order bits (D4 to D7) and are supplied to the terminals Na and Nb. By turning on the switch Sinit and connecting switches Sse10 to Sse13 to the Na side, the voltage at a node (Nc) of the non-inverting input side of the voltage follower is initialized to the voltage at terminal Na and the respective terminal voltages across the four capacitors C/8, C/4, C/2 and C are reset.
Next, when the voltages at the terminals Na and Nb are selectively supplied to the four capacitors C/8, C/4, C/2 and C by the lower-order bits (D0 to D3), redistribution of electric charge occurs, a voltage that is the result of the voltage between the voltage at terminal Na and the voltage at terminal Nb being divided by 16 is supplied to the node Nc and a voltage that is the same as that at node Nc is output by the voltage follower. Accordingly, owing to the selection of two mutually adjacent voltages by the higher-order bits and division by 16 by means of the lower-order bits, outputs having 16×16=256 levels can be obtained.
In accordance with the conventional art, the number of reference voltages from the resistor string can be reduced in comparison with the number of output voltage levels. More specifically, if we let m represent the number of reference voltages and n the number of capacitors, then (m−1)×2n outputs can be obtained.
By applying this technique to the grayscale voltage generating circuit 983, decoders 984 and amplifiers 985, therefore, the area of the data driver can be reduced and a reduction in cost achieved.
[Non-Patent Document 1]
Yoshiyuki Takeishi, Edited by Hisashi Hara, “Foundations of MOS Integrated Circuits”, Ultra LSI Introduction Series 5, p. 164, FIG. 5-39, Kindai Kagakusha, May 30, 2002